The design and implementation of a first-generation CELL processor

Pham, D.; Asano, S.; Bolliger, M.; Day, Michael; Peter Hofstee, H.; Johns, C.; Kahle, J.; Kameyama, Atsushi; Keaty, J.; Masubuchi, Yoshio; Riley, M.; Shippy, D.; Stasiak, D.; Suzuoki, M.; Wang, Mingjun; Warnock, J.; Weitzel, S.; Wendel, D.; Yamazaki, T.; Yazawa, Kazuaki

doi:10.1109/isscc.2005.1493930

Public

The design and implementation of a first-generation CELL processor

Published • Aug 30, 2005

Authors:

D. Pham

S. Asano

M. Bolliger

Abstract

A CELL processor is a multi-core chip consisting of a 64b power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximi...

Subject

Computer science

Modularity (biology)

Embedded system

Finding related papers...

Discussions

(0)

No comments yet

Be the first to share your thoughts!